mirror of
https://github.com/intrepidcs/libicsneo.git
synced 2026-08-05 01:18:36 +02:00
C2: Add ChipVersions
Also fixes some formatting issues.
This commit is contained in:
David Rebbe
committed by
Kyle Schwarz
Kyle Schwarz
parent
e926e10dc5
commit
c3762bbf22
@@ -4,6 +4,7 @@
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#include <icsneo/icsneoc2messages.h>
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#include "../../api/icsneoc2/icsneoc2_internal.h"
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#include <icsneo/device/devicetype.h>
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#include <icsneo/device/chipid.h>
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#include <icsneo/communication/message/linmessage.h>
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#include <icsneo/communication/message/canmessage.h>
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#include <icsneo/communication/message/canerrormessage.h>
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@@ -713,6 +714,360 @@ TEST(icsneoc2, test_icsneoc2_netid_t)
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ASSERT_EQ(icsneoc2_netid_maxsize, 571);
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}
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TEST(icsneoc2, test_icsneoc2_chip_id_t)
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{
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ASSERT_EQ(icsneoc2_chip_id_neovifire_mchip, 0);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_lchip, 1);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_uchip, 2);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_jchip, 3);
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ASSERT_EQ(icsneoc2_chip_id_valuecan3_mchip, 4);
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ASSERT_EQ(icsneoc2_chip_id_neoviecu_mpic, 6);
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ASSERT_EQ(icsneoc2_chip_id_neoviievb_mpic, 7);
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ASSERT_EQ(icsneoc2_chip_id_neovipendant_mpic, 8);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_vnet_mchip, 9);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_vnet_lchip, 10);
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ASSERT_EQ(icsneoc2_chip_id_neoviplasma_core, 11);
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ASSERT_EQ(icsneoc2_chip_id_neoviplasma_hid, 12);
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ASSERT_EQ(icsneoc2_chip_id_neovianalog_mpic, 13);
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ASSERT_EQ(icsneoc2_chip_id_neoviplasma_analog_core, 14);
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ASSERT_EQ(icsneoc2_chip_id_neoviplasma_flexray_core, 15);
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ASSERT_EQ(icsneoc2_chip_id_neoviplasma_core_1_12, 16);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_slave_vnet_mchip, 17);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_slave_vnet_lchip, 18);
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ASSERT_EQ(icsneoc2_chip_id_neoviion_core, 19);
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ASSERT_EQ(icsneoc2_chip_id_neoviion_hid, 20);
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ASSERT_EQ(icsneoc2_chip_id_neoviion_core_loader, 21);
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ASSERT_EQ(icsneoc2_chip_id_neoviion_hid_loader, 22);
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ASSERT_EQ(icsneoc2_chip_id_neoviion_fpga_bit, 23);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_vnet_ep_mchip, 24);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_vnet_ep_lchip, 25);
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ASSERT_EQ(icsneoc2_chip_id_neovianalogout_mchip, 26);
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ASSERT_EQ(icsneoc2_chip_id_neovimost25_mchip, 27);
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ASSERT_EQ(icsneoc2_chip_id_neovimost50_mchip, 28);
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ASSERT_EQ(icsneoc2_chip_id_neovimost150_mchip, 29);
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ASSERT_EQ(icsneoc2_chip_id_valuecan4_4_mchip, 30);
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ASSERT_EQ(icsneoc2_chip_id_valuecan4_4_schip, 31);
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ASSERT_EQ(icsneoc2_chip_id_cmprobe_zynq, 33);
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ASSERT_EQ(icsneoc2_chip_id_eevb_stm32, 34);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_slave_vnet_ep_mchip, 35);
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ASSERT_EQ(icsneoc2_chip_id_neovifire_slave_vnet_ep_lchip, 36);
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ASSERT_EQ(icsneoc2_chip_id_radstar_mchip, 37);
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ASSERT_EQ(icsneoc2_chip_id_valuecanrf_mchip, 38);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_mchip, 39);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_cchip, 40);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_core, 41);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_blechip, 42);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_zynq, 43);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_securitychip, 44);
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ASSERT_EQ(icsneoc2_chip_id_radgalaxy_zynq, 45);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnet_mchip, 46);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_slave_vnet_a_mchip, 47);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_slave_vnet_a_cchip, 48);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnet_cchip, 49);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnet_core, 50);
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ASSERT_EQ(icsneoc2_chip_id_radstar2_zynq, 51);
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ASSERT_EQ(icsneoc2_chip_id_vividcan_mchip, 52);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2sim_mchip, 53);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnetz_mchip, 54);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnetz_zynq, 55);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_slave_vnetz_a_mchip, 56);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_slave_vnetz_a_zynq, 57);
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ASSERT_EQ(icsneoc2_chip_id_vividcan_ext_flash, 58);
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ASSERT_EQ(icsneoc2_chip_id_vividcan_nrf52, 59);
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ASSERT_EQ(icsneoc2_chip_id_cmprobe_zynq_unused, 60);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2pro_mchip, 61);
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ASSERT_EQ(icsneoc2_chip_id_valuecan4_1_mchip, 62);
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ASSERT_EQ(icsneoc2_chip_id_valuecan4_2_mchip, 63);
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ASSERT_EQ(icsneoc2_chip_id_valuecan4_4_2el_core, 64);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2pro_schip, 65);
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ASSERT_EQ(icsneoc2_chip_id_valuecan4_2el_mchip, 67);
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ASSERT_EQ(icsneoc2_chip_id_neoecuavbtsn_mchip, 68);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2pro_core, 69);
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ASSERT_EQ(icsneoc2_chip_id_radsupermoon_zynq, 70);
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ASSERT_EQ(icsneoc2_chip_id_radmoon2_zynq, 71);
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ASSERT_EQ(icsneoc2_chip_id_vividcanpro_mchip, 72);
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ASSERT_EQ(icsneoc2_chip_id_vividcanpro_ext_flash, 73);
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ASSERT_EQ(icsneoc2_chip_id_radpluto_mchip, 74);
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ASSERT_EQ(icsneoc2_chip_id_radmars_zynq, 75);
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ASSERT_EQ(icsneoc2_chip_id_neoecu12_mchip, 76);
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ASSERT_EQ(icsneoc2_chip_id_radiocanhub_mchip, 77);
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ASSERT_EQ(icsneoc2_chip_id_flexray_vnetz_zchip, 78);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2_lcbadge_mchip, 79);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2_lcbadge_schip, 80);
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ASSERT_EQ(icsneoc2_chip_id_radmoonduo_mchip, 81);
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ASSERT_EQ(icsneoc2_chip_id_neovifire3_zchip, 82);
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ASSERT_EQ(icsneoc2_chip_id_flexray_vnetz_fchip, 83);
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ASSERT_EQ(icsneoc2_chip_id_radjupiter_mchip, 84);
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ASSERT_EQ(icsneoc2_chip_id_valuecan4industrial_mchip, 85);
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ASSERT_EQ(icsneoc2_chip_id_etherbadge_mchip, 86);
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ASSERT_EQ(icsneoc2_chip_id_radmars_3_zynq, 87);
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ASSERT_EQ(icsneoc2_chip_id_radgigastar_usbz_zynq, 88);
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ASSERT_EQ(icsneoc2_chip_id_radgigastar_zynq, 89);
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ASSERT_EQ(icsneoc2_chip_id_rad4g_mchip, 90);
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ASSERT_EQ(icsneoc2_chip_id_neovifire3_schip, 91);
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ASSERT_EQ(icsneoc2_chip_id_radepsilon_mchip, 92);
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ASSERT_EQ(icsneoc2_chip_id_rada2b_zchip, 93);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2dev_mchip, 94);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2dev_schip, 95);
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ASSERT_EQ(icsneoc2_chip_id_neoobd2simdoip_mchip, 96);
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ASSERT_EQ(icsneoc2_chip_id_sfpmodule_88q2112_mchip, 97);
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ASSERT_EQ(icsneoc2_chip_id_radepsilont_mchip, 98);
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ASSERT_EQ(icsneoc2_chip_id_radepsilonexpress_mchip, 99);
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ASSERT_EQ(icsneoc2_chip_id_radproxima_mchip, 100);
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ASSERT_EQ(icsneoc2_chip_id_newdevice57_zchip, 101);
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ASSERT_EQ(icsneoc2_chip_id_rad_galaxy_2_zmpchip_id, 102);
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ASSERT_EQ(icsneoc2_chip_id_newdevice59_mchip, 103);
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ASSERT_EQ(icsneoc2_chip_id_radmoon2_z7010_zynq, 104);
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ASSERT_EQ(icsneoc2_chip_id_neovifire2_core_sg4, 105);
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ASSERT_EQ(icsneoc2_chip_id_radbms_mchip, 106);
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ASSERT_EQ(icsneoc2_chip_id_radmoon2_zl_mchip, 107);
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ASSERT_EQ(icsneoc2_chip_id_radgigastar_usbz_z7010_zynq, 108);
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ASSERT_EQ(icsneoc2_chip_id_neovifire3_linux, 109);
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ASSERT_EQ(icsneoc2_chip_id_radgigastar_usbz_z7007s_zynq, 110);
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ASSERT_EQ(icsneoc2_chip_id_vem_01_8dw_zchip, 111);
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ASSERT_EQ(icsneoc2_chip_id_radgalaxy_ffg_zynq, 112);
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ASSERT_EQ(icsneoc2_chip_id_radmoon3_mchip, 113);
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ASSERT_EQ(icsneoc2_chip_id_radcomet_zynq, 114);
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ASSERT_EQ(icsneoc2_chip_id_vem_02_fr_zchip, 115);
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ASSERT_EQ(icsneoc2_chip_id_rada2b_revb_zchip, 116);
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ASSERT_EQ(icsneoc2_chip_id_radgigastar_ffg_zynq, 117);
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ASSERT_EQ(icsneoc2_chip_id_vem_02_fr_fchip, 118);
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ASSERT_EQ(icsneoc2_chip_id_connect_zchip, 121);
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ASSERT_EQ(icsneoc2_chip_id_sfpmodule_88q2221_mchip, 122);
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ASSERT_EQ(icsneoc2_chip_id_radgalaxy2_sysmon_chip, 123);
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ASSERT_EQ(icsneoc2_chip_id_sfpmodule_88q3244_mchip, 124);
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ASSERT_EQ(icsneoc2_chip_id_radcomet3_zchip, 125);
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ASSERT_EQ(icsneoc2_chip_id_connect_linux, 126);
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ASSERT_EQ(icsneoc2_chip_id_sfpmodule_lan8670_mchip, 127);
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ASSERT_EQ(icsneoc2_chip_id_vem_04_t1s_lin_zchip, 129);
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ASSERT_EQ(icsneoc2_chip_id_radmoont1s_zchip, 130);
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ASSERT_EQ(icsneoc2_chip_id_radgigastar2_zynq, 131);
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ASSERT_EQ(icsneoc2_chip_id_sfpmodule_ent11100_mchip, 132);
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ASSERT_EQ(icsneoc2_chip_id_radgemini_mchip, 135);
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ASSERT_EQ(icsneoc2_chip_id_maxsize, 136);
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ASSERT_EQ(icsneoc2_chip_id_invalid, 255);
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ASSERT_EQ(sizeof(icsneoc2_chip_id_t), sizeof(uint8_t));
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}
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TEST(icsneoc2, test_chip_id_enum_alignment)
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{
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_MCHIP), icsneoc2_chip_id_neovifire_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_LCHIP), icsneoc2_chip_id_neovifire_lchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_UCHIP), icsneoc2_chip_id_neovifire_uchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_JCHIP), icsneoc2_chip_id_neovifire_jchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN3_MCHIP), icsneoc2_chip_id_valuecan3_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIECU_MPIC), icsneoc2_chip_id_neoviecu_mpic);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIIEVB_MPIC), icsneoc2_chip_id_neoviievb_mpic);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPENDANT_MPIC), icsneoc2_chip_id_neovipendant_mpic);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_VNET_MCHIP), icsneoc2_chip_id_neovifire_vnet_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_VNET_LCHIP), icsneoc2_chip_id_neovifire_vnet_lchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_Core), icsneoc2_chip_id_neoviplasma_core);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_HID), icsneoc2_chip_id_neoviplasma_hid);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIANALOG_MPIC), icsneoc2_chip_id_neovianalog_mpic);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_ANALOG_Core), icsneoc2_chip_id_neoviplasma_analog_core);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_FlexRay_Core), icsneoc2_chip_id_neoviplasma_flexray_core);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_Core_1_12), icsneoc2_chip_id_neoviplasma_core_1_12);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_Slave_VNET_MCHIP), icsneoc2_chip_id_neovifire_slave_vnet_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_Slave_VNET_LCHIP), icsneoc2_chip_id_neovifire_slave_vnet_lchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_Core), icsneoc2_chip_id_neoviion_core);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_HID), icsneoc2_chip_id_neoviion_hid);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_Core_Loader), icsneoc2_chip_id_neoviion_core_loader);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_HID_Loader), icsneoc2_chip_id_neoviion_hid_loader);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_FPGA_BIT), icsneoc2_chip_id_neoviion_fpga_bit);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_VNET_EP_MCHIP), icsneoc2_chip_id_neovifire_vnet_ep_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_VNET_EP_LCHIP), icsneoc2_chip_id_neovifire_vnet_ep_lchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIAnalogOut_MCHIP), icsneoc2_chip_id_neovianalogout_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIMOST25_MCHIP), icsneoc2_chip_id_neovimost25_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIMOST50_MCHIP), icsneoc2_chip_id_neovimost50_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIMOST150_MCHIP), icsneoc2_chip_id_neovimost150_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_4_MCHIP), icsneoc2_chip_id_valuecan4_4_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_4_SCHIP), icsneoc2_chip_id_valuecan4_4_schip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::cmProbe_ZYNQ), icsneoc2_chip_id_cmprobe_zynq);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::EEVB_STM32), icsneoc2_chip_id_eevb_stm32);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_Slave_VNET_EP_MCHIP), icsneoc2_chip_id_neovifire_slave_vnet_ep_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_Slave_VNET_EP_LCHIP), icsneoc2_chip_id_neovifire_slave_vnet_ep_lchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADStar_MCHIP), icsneoc2_chip_id_radstar_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCANrf_MCHIP), icsneoc2_chip_id_valuecanrf_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_MCHIP), icsneoc2_chip_id_neovifire2_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_CCHIP), icsneoc2_chip_id_neovifire2_cchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Core), icsneoc2_chip_id_neovifire2_core);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_BLECHIP), icsneoc2_chip_id_neovifire2_blechip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_ZYNQ), icsneoc2_chip_id_neovifire2_zynq);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_SECURITYCHIP), icsneoc2_chip_id_neovifire2_securitychip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGalaxy_ZYNQ), icsneoc2_chip_id_radgalaxy_zynq);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNET_MCHIP), icsneoc2_chip_id_neovifire2_vnet_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Slave_VNET_A_MCHIP), icsneoc2_chip_id_neovifire2_slave_vnet_a_mchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Slave_VNET_A_CCHIP), icsneoc2_chip_id_neovifire2_slave_vnet_a_cchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNET_CCHIP), icsneoc2_chip_id_neovifire2_vnet_cchip);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNET_Core), icsneoc2_chip_id_neovifire2_vnet_core);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADStar2_ZYNQ), icsneoc2_chip_id_radstar2_zynq);
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ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCAN_MCHIP), icsneoc2_chip_id_vividcan_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2SIM_MCHIP), icsneoc2_chip_id_neoobd2sim_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNETZ_MCHIP), icsneoc2_chip_id_neovifire2_vnetz_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNETZ_ZYNQ), icsneoc2_chip_id_neovifire2_vnetz_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Slave_VNETZ_A_MCHIP), icsneoc2_chip_id_neovifire2_slave_vnetz_a_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Slave_VNETZ_A_ZYNQ), icsneoc2_chip_id_neovifire2_slave_vnetz_a_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCAN_EXT_FLASH), icsneoc2_chip_id_vividcan_ext_flash);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCAN_NRF52), icsneoc2_chip_id_vividcan_nrf52);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::cmProbe_ZYNQ_Unused), icsneoc2_chip_id_cmprobe_zynq_unused);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2PRO_MCHIP), icsneoc2_chip_id_neoobd2pro_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_1_MCHIP), icsneoc2_chip_id_valuecan4_1_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_2_MCHIP), icsneoc2_chip_id_valuecan4_2_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_4_2EL_Core), icsneoc2_chip_id_valuecan4_4_2el_core);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2PRO_SCHIP), icsneoc2_chip_id_neoobd2pro_schip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_2EL_MCHIP), icsneoc2_chip_id_valuecan4_2el_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoECUAVBTSN_MCHIP), icsneoc2_chip_id_neoecuavbtsn_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2PRO_Core), icsneoc2_chip_id_neoobd2pro_core);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADSupermoon_ZYNQ), icsneoc2_chip_id_radsupermoon_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoon2_ZYNQ), icsneoc2_chip_id_radmoon2_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCANPRO_MCHIP), icsneoc2_chip_id_vividcanpro_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCANPRO_EXT_FLASH), icsneoc2_chip_id_vividcanpro_ext_flash);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADPluto_MCHIP), icsneoc2_chip_id_radpluto_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMars_ZYNQ), icsneoc2_chip_id_radmars_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoECU12_MCHIP), icsneoc2_chip_id_neoecu12_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADIOCANHUB_MCHIP), icsneoc2_chip_id_radiocanhub_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::FlexRay_VNETZ_ZCHIP), icsneoc2_chip_id_flexray_vnetz_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2_LCBADGE_MCHIP), icsneoc2_chip_id_neoobd2_lcbadge_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2_LCBADGE_SCHIP), icsneoc2_chip_id_neoobd2_lcbadge_schip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoonDuo_MCHIP), icsneoc2_chip_id_radmoonduo_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE3_ZCHIP), icsneoc2_chip_id_neovifire3_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::FlexRay_VNETZ_FCHIP), icsneoc2_chip_id_flexray_vnetz_fchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADJupiter_MCHIP), icsneoc2_chip_id_radjupiter_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4Industrial_MCHIP), icsneoc2_chip_id_valuecan4industrial_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::EtherBADGE_MCHIP), icsneoc2_chip_id_etherbadge_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMars_3_ZYNQ), icsneoc2_chip_id_radmars_3_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_USBZ_ZYNQ), icsneoc2_chip_id_radgigastar_usbz_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_ZYNQ), icsneoc2_chip_id_radgigastar_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RAD4G_MCHIP), icsneoc2_chip_id_rad4g_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE3_SCHIP), icsneoc2_chip_id_neovifire3_schip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADEpsilon_MCHIP), icsneoc2_chip_id_radepsilon_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADA2B_ZCHIP), icsneoc2_chip_id_rada2b_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2Dev_MCHIP), icsneoc2_chip_id_neoobd2dev_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2Dev_SCHIP), icsneoc2_chip_id_neoobd2dev_schip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2SIMDoIP_MCHIP), icsneoc2_chip_id_neoobd2simdoip_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_88q2112_MCHIP), icsneoc2_chip_id_sfpmodule_88q2112_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADEpsilonT_MCHIP), icsneoc2_chip_id_radepsilont_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADEpsilonExpress_MCHIP), icsneoc2_chip_id_radepsilonexpress_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADProxima_MCHIP), icsneoc2_chip_id_radproxima_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::NewDevice57_ZCHIP), icsneoc2_chip_id_newdevice57_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RAD_GALAXY_2_ZMPCHIP_ID), icsneoc2_chip_id_rad_galaxy_2_zmpchip_id);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::NewDevice59_MCHIP), icsneoc2_chip_id_newdevice59_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoon2_Z7010_ZYNQ), icsneoc2_chip_id_radmoon2_z7010_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Core_SG4), icsneoc2_chip_id_neovifire2_core_sg4);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADBMS_MCHIP), icsneoc2_chip_id_radbms_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoon2_ZL_MCHIP), icsneoc2_chip_id_radmoon2_zl_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_USBZ_Z7010_ZYNQ), icsneoc2_chip_id_radgigastar_usbz_z7010_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE3_LINUX), icsneoc2_chip_id_neovifire3_linux);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_USBZ_Z7007S_ZYNQ), icsneoc2_chip_id_radgigastar_usbz_z7007s_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VEM_01_8DW_ZCHIP), icsneoc2_chip_id_vem_01_8dw_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGalaxy_FFG_Zynq), icsneoc2_chip_id_radgalaxy_ffg_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoon3_MCHIP), icsneoc2_chip_id_radmoon3_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADComet_ZYNQ), icsneoc2_chip_id_radcomet_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VEM_02_FR_ZCHIP), icsneoc2_chip_id_vem_02_fr_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADA2B_REVB_ZCHIP), icsneoc2_chip_id_rada2b_revb_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_FFG_ZYNQ), icsneoc2_chip_id_radgigastar_ffg_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VEM_02_FR_FCHIP), icsneoc2_chip_id_vem_02_fr_fchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::Connect_ZCHIP), icsneoc2_chip_id_connect_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_88q2221_MCHIP), icsneoc2_chip_id_sfpmodule_88q2221_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGALAXY2_SYSMON_CHIP), icsneoc2_chip_id_radgalaxy2_sysmon_chip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_88q3244_MCHIP), icsneoc2_chip_id_sfpmodule_88q3244_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADCOMET3_ZCHIP), icsneoc2_chip_id_radcomet3_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::Connect_LINUX), icsneoc2_chip_id_connect_linux);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_lan8670_MCHIP), icsneoc2_chip_id_sfpmodule_lan8670_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VEM_04_T1S_LIN_ZCHIP), icsneoc2_chip_id_vem_04_t1s_lin_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMOONT1S_ZCHIP), icsneoc2_chip_id_radmoont1s_zchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar2_ZYNQ), icsneoc2_chip_id_radgigastar2_zynq);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_ent11100_MCHIP), icsneoc2_chip_id_sfpmodule_ent11100_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGemini_MCHIP), icsneoc2_chip_id_radgemini_mchip);
|
||||
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::Invalid), icsneoc2_chip_id_invalid);
|
||||
}
|
||||
|
||||
TEST(icsneoc2, test_icsneoc2_chip_versions_invalid_parameters)
|
||||
{
|
||||
size_t count = 0;
|
||||
icsneoc2_chip_versions_t* chip_versions = nullptr;
|
||||
|
||||
// enumerate: NULL device
|
||||
ASSERT_EQ(icsneoc2_error_invalid_parameters, icsneoc2_device_chip_versions_enumerate(NULL, &chip_versions, false, &count));
|
||||
|
||||
// props_get: NULL handle
|
||||
uint8_t major = 0, minor = 0, maintenance = 0, build = 0;
|
||||
char name[32] = {0};
|
||||
size_t name_length = sizeof(name);
|
||||
ASSERT_EQ(icsneoc2_error_invalid_parameters, icsneoc2_chip_versions_props_get(NULL, name, &name_length, &major, &minor, &maintenance, &build));
|
||||
|
||||
// free: NULL handle
|
||||
ASSERT_EQ(icsneoc2_error_invalid_parameters, icsneoc2_chip_versions_free(NULL));
|
||||
|
||||
// next: NULL handle returns NULL
|
||||
ASSERT_EQ(nullptr, icsneoc2_chip_versions_next(NULL));
|
||||
}
|
||||
|
||||
TEST(icsneoc2, test_icsneoc2_chip_versions_props_get)
|
||||
{
|
||||
// Build an in-memory list of two chip_versions nodes
|
||||
icsneoc2_chip_versions_t second{};
|
||||
second.version_report.id = icsneo::ChipID::RADGemini_MCHIP;
|
||||
second.version_report.name = "second";
|
||||
second.version_report.major = 9;
|
||||
second.version_report.minor = 8;
|
||||
second.version_report.maintenance = 7;
|
||||
second.version_report.build = 6;
|
||||
second.next = nullptr;
|
||||
|
||||
icsneoc2_chip_versions_t first{};
|
||||
first.version_report.id = icsneo::ChipID::neoVIFIRE_MCHIP;
|
||||
first.version_report.name = "first";
|
||||
first.version_report.major = 1;
|
||||
first.version_report.minor = 2;
|
||||
first.version_report.maintenance = 3;
|
||||
first.version_report.build = 4;
|
||||
first.next = &second;
|
||||
|
||||
// next() walks the list
|
||||
ASSERT_EQ(&second, icsneoc2_chip_versions_next(&first));
|
||||
ASSERT_EQ(nullptr, icsneoc2_chip_versions_next(&second));
|
||||
|
||||
// props_get: full extraction
|
||||
char name[32] = {0};
|
||||
size_t name_length = sizeof(name);
|
||||
uint8_t major = 0, minor = 0, maintenance = 0, build = 0;
|
||||
ASSERT_EQ(icsneoc2_error_success, icsneoc2_chip_versions_props_get(&first, name, &name_length, &major, &minor, &maintenance, &build));
|
||||
ASSERT_STREQ(name, "first");
|
||||
ASSERT_EQ(name_length, 5u);
|
||||
ASSERT_EQ(major, 1);
|
||||
ASSERT_EQ(minor, 2);
|
||||
ASSERT_EQ(maintenance, 3);
|
||||
ASSERT_EQ(build, 4);
|
||||
|
||||
// props_get: all output pointers optional (NULL allowed)
|
||||
ASSERT_EQ(icsneoc2_error_success, icsneoc2_chip_versions_props_get(&second, NULL, NULL, NULL, NULL, NULL, NULL));
|
||||
|
||||
// props_get: only some output pointers
|
||||
major = 0;
|
||||
ASSERT_EQ(icsneoc2_error_success, icsneoc2_chip_versions_props_get(&second, NULL, NULL, &major, NULL, NULL, NULL));
|
||||
ASSERT_EQ(major, 9);
|
||||
|
||||
// props_get: name buffer too small returns string_copy_failed
|
||||
char tiny[2] = {0};
|
||||
size_t tiny_length = sizeof(tiny);
|
||||
ASSERT_EQ(icsneoc2_error_string_copy_failed, icsneoc2_chip_versions_props_get(&first, tiny, &tiny_length, NULL, NULL, NULL, NULL));
|
||||
}
|
||||
|
||||
TEST(icsneoc2, test_icsneoc2_chip_versions_free_list)
|
||||
{
|
||||
// Allocate a two-node list the same way the API does, so free() walks and deletes it.
|
||||
auto* head = new icsneoc2_chip_versions_t{};
|
||||
head->version_report.name = "a";
|
||||
head->next = new icsneoc2_chip_versions_t{};
|
||||
head->next->version_report.name = "b";
|
||||
head->next->next = nullptr;
|
||||
|
||||
ASSERT_EQ(icsneoc2_error_success, icsneoc2_chip_versions_free(head));
|
||||
}
|
||||
|
||||
TEST(icsneoc2, test_icsneoc2_open_options_default)
|
||||
{
|
||||
icsneoc2_open_options_t expected = ICSNEOC2_OPEN_OPTIONS_GO_ONLINE | ICSNEOC2_OPEN_OPTIONS_SYNC_RTC | ICSNEOC2_OPEN_OPTIONS_ENABLE_AUTO_UPDATE;
|
||||
|
||||
Reference in New Issue
Block a user