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C2: Add ChipVersions 

Also fixes some formatting issues.
pull/86/head
David Rebbe 2026-05-14 17:39:39 +00:00 committed by Kyle Schwarz
parent e926e10dc5
commit c3762bbf22
9 changed files with 834 additions and 138 deletions
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97
api/icsneoc2/icsneoc2.cpp
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@ -251,12 +251,12 @@ icsneoc2_error_t icsneoc2_device_open_serial(const char* serial, icsneoc2_open_o
std::string_view target(serial);
for(auto* cur = devs; cur; cur = cur->next) {
if(cur->device && cur->device->getSerial() == target) {
if (res = icsneoc2_device_create(cur, device); res != icsneoc2_error_success) {
if(res = icsneoc2_device_create(cur, device); res != icsneoc2_error_success) {
icsneoc2_enumeration_free(devs);
return res;
}
res = open_device_with_options((*device)->device, options);
if (res != icsneoc2_error_success) {
if(res != icsneoc2_error_success) {
icsneoc2_device_free(*device);
*device = nullptr;
}
@ -279,12 +279,12 @@ icsneoc2_error_t icsneoc2_device_open_first(icsneoc2_devicetype_t device_type, i
}
for(auto* cur = devs; cur; cur = cur->next) {
if(cur->device && !cur->device->isOpen()) {
if (res = icsneoc2_device_create(cur, device); res != icsneoc2_error_success) {
if(res = icsneoc2_device_create(cur, device); res != icsneoc2_error_success) {
icsneoc2_enumeration_free(devs);
return res;
}
res = open_device_with_options((*device)->device, options);
if (res != icsneoc2_error_success) {
if(res != icsneoc2_error_success) {
icsneoc2_device_free(*device);
*device = nullptr;
}
@ -302,7 +302,7 @@ icsneoc2_error_t icsneoc2_device_reconnect(icsneoc2_device_t* device, icsneoc2_o
return res;
}
// If the device is currently open, close it first before trying to reconnect
if (device->device->isOpen()) {
if(device->device->isOpen()) {
res = icsneoc2_device_close(device);
if(res != icsneoc2_error_success) {
return res;
@ -342,7 +342,7 @@ icsneoc2_error_t icsneoc2_device_free(icsneoc2_device_t* device) {
if(res != icsneoc2_error_success) {
return res;
}
if (device->device->isOpen()) {
if(device->device->isOpen()) {
res = icsneoc2_device_close(device);
if(res != icsneoc2_error_success) {
return res;
@ -671,10 +671,10 @@ icsneoc2_error_t icsneoc2_device_tc10_status_get(const icsneoc2_device_t* device
if(!cpp_status.has_value()) {
return icsneoc2_error_invalid_type;
}
if (sleep_status) {
if(sleep_status) {
*sleep_status = static_cast<icsneoc2_tc10_sleep_status_t>(cpp_status->sleepStatus);
}
if (wake_status) {
if(wake_status) {
*wake_status = static_cast<icsneoc2_tc10_wake_status_t>(cpp_status->wakeStatus);
}
return icsneoc2_error_success;
@ -1208,3 +1208,84 @@ icsneoc2_error_t icsneoc2_script_status_max_coremini_size_kb_get(const icsneoc2_
*value = script_status->status->maxCoreminiSizeKB;
return icsneoc2_error_success;
}
icsneoc2_error_t icsneoc2_device_chip_versions_enumerate(const icsneoc2_device_t* device, icsneoc2_chip_versions_t** chip_versions, bool refresh, size_t* count) {
auto res = icsneoc2_device_is_valid(device);
if(res != icsneoc2_error_success) {
return res;
}
if(!chip_versions) {
return icsneoc2_error_invalid_parameters;
}
auto version_reports = device->device->getChipVersions(refresh);
if(count) {
*count = version_reports.size();
}
icsneoc2_chip_versions_t* head = nullptr;
icsneoc2_chip_versions_t* tail = nullptr;
for(auto& version_report : version_reports) {
auto* node = new (std::nothrow) icsneoc2_chip_versions_t;
if(!node) {
icsneoc2_chip_versions_free(head);
return icsneoc2_error_out_of_memory;
}
node->version_report = version_report;
node->next = nullptr;
if(!head) {
head = node;
} else {
tail->next = node;
}
tail = node;
}
*chip_versions = head;
return icsneoc2_error_success;
}
icsneoc2_error_t icsneoc2_chip_versions_free(icsneoc2_chip_versions_t* chip_versions) {
if(!chip_versions) {
return icsneoc2_error_invalid_parameters;
}
while(chip_versions) {
auto* next = chip_versions->next;
delete chip_versions;
chip_versions = next;
}
return icsneoc2_error_success;
}
icsneoc2_chip_versions_t* icsneoc2_chip_versions_next(const icsneoc2_chip_versions_t* chip_versions) {
if(!chip_versions) {
return nullptr;
}
return chip_versions->next;
}
icsneoc2_error_t icsneoc2_chip_versions_props_get(const icsneoc2_chip_versions_t* chip_versions, char* name, size_t* name_length, uint8_t* major, uint8_t* minor, uint8_t* maintenance, uint8_t* build) {
if(!chip_versions) {
return icsneoc2_error_invalid_parameters;
}
auto& report = chip_versions->version_report;
if(name && name_length) {
if(!safe_str_copy(name,name_length, report.name)) {
return icsneoc2_error_string_copy_failed;
}
}
if(major) {
*major = report.major;
}
if(minor) {
*minor = report.minor;
}
if(maintenance) {
*maintenance = report.maintenance;
}
if(build) {
*build = report.build;
}
return icsneoc2_error_success;
}

5
api/icsneoc2/icsneoc2_internal.h
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@ -38,6 +38,11 @@ typedef struct icsneoc2_script_status_t {
std::shared_ptr<ScriptStatusMessage> status;
} icsneoc2_script_status_t;
typedef struct icsneoc2_chip_versions_t {
VersionReport version_report;
icsneoc2_chip_versions_t* next;
} icsneoc2_chip_versions_t;
/**
* Safely copies a std::string to a char array.
*

5
examples/CMakeLists.txt
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@ -6,6 +6,7 @@ option(LIBICSNEO_BUILD_C2_READ_MESSAGES_EXAMPLE "Build the C2 read messages exam
option(LIBICSNEO_BUILD_C2_DISKFORMAT_EXAMPLE "Build the C2 disk format example." ON)
option(LIBICSNEO_BUILD_C2_RECONNECT_EXAMPLE "Build the C2 reconnect example." ON)
option(LIBICSNEO_BUILD_C2_DEVICE_INFO_EXAMPLE "Build the C2 device info example." ON)
option(LIBICSNEO_BUILD_C2_CHIP_VERSIONS_EXAMPLE "Build the C2 chip versions example." ON)
option(LIBICSNEO_BUILD_C2_LIN_EXAMPLE "Build the C2 LIN example." ON)
option(LIBICSNEO_BUILD_C2_LIN_TRANSMIT_EXAMPLE "Build the C2 LIN transmit example." ON)
option(LIBICSNEO_BUILD_C2_ETHERNET_TRANSMIT_EXAMPLE "Build the C2 ethernet transmit example." ON)
@ -63,6 +64,10 @@ if(LIBICSNEO_BUILD_C2_DEVICE_INFO_EXAMPLE)
add_subdirectory(c2/device_info)
endif()
if(LIBICSNEO_BUILD_C2_CHIP_VERSIONS_EXAMPLE)
add_subdirectory(c2/chip_versions)
endif()
if(LIBICSNEO_BUILD_C2_LIN_EXAMPLE)
add_subdirectory(c2/lin)
endif()

6
examples/c2/chip_versions/CMakeLists.txt 100644
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@ -0,0 +1,6 @@
add_executable(libicsneoc2-chip-versions-example src/main.c)
target_link_libraries(libicsneoc2-chip-versions-example icsneoc2-static)
if(WIN32)
target_compile_definitions(libicsneoc2-chip-versions-example PRIVATE _CRT_SECURE_NO_WARNINGS)
endif()

59
examples/c2/chip_versions/src/main.c 100644
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@ -0,0 +1,59 @@
#include <icsneo/icsneoc2.h>
#include <stdio.h>
#include <inttypes.h>
int print_error_code(const char* message, icsneoc2_error_t error) {
char error_str[64];
size_t error_str_len = sizeof(error_str);
icsneoc2_error_t res = icsneoc2_error_code_get(error, error_str, &error_str_len);
if(res != icsneoc2_error_success) {
printf("%s: Failed to get string for error code %u with error code %u\n", message, error, res);
return (int)res;
}
printf("%s: \"%s\" (%u)\n", message, error_str, error);
return (int)error;
}
int main() {
icsneoc2_error_t res;
icsneoc2_device_t* device = NULL;
res = icsneoc2_device_open_first(0, icsneoc2_open_options_default, &device);
if(res != icsneoc2_error_success) {
return print_error_code("Failed to open first device", res);
}
char description[128] = {0};
size_t description_length = sizeof(description);
icsneoc2_device_description_get(device, description, &description_length);
printf("Opened device: %s\n\n", description);
size_t count = 0;
icsneoc2_chip_versions_t* chip_versions = NULL;
res = icsneoc2_device_chip_versions_enumerate(device, &chip_versions, true, &count);
if(res != icsneoc2_error_success) {
print_error_code("Failed to enumerate chip versions", res);
icsneoc2_device_close(device);
icsneoc2_device_free(device);
return 1;
}
printf("Found %zu chip version(s):\n", count);
for(icsneoc2_chip_versions_t* cur = chip_versions; cur; cur = icsneoc2_chip_versions_next(cur)) {
char name[64] = {0};
size_t name_length = sizeof(name);
uint8_t major = 0, minor = 0, maintenance = 0, build = 0;
res = icsneoc2_chip_versions_props_get(cur, name, &name_length, &major, &minor, &maintenance, &build);
if(res != icsneoc2_error_success) {
print_error_code("Failed to get chip version properties", res);
continue;
}
printf(" %s: %u.%u.%u.%u\n", name, major, minor, maintenance, build);
}
icsneoc2_chip_versions_free(chip_versions);
icsneoc2_device_close(device);
icsneoc2_device_free(device);
return 0;
}

262
include/icsneo/device/chipid.h
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@ -1,142 +1,144 @@
#ifndef __CHIP_ID_H_
#define __CHIP_ID_H_
#include "icsneo/icsneoc2types.h"
#ifdef __cplusplus
#include <cstdint>
namespace icsneo {
enum class ChipID : uint8_t {
neoVIFIRE_MCHIP = 0,
neoVIFIRE_LCHIP = 1,
neoVIFIRE_UCHIP = 2,
neoVIFIRE_JCHIP = 3,
ValueCAN3_MCHIP = 4,
neoVIECU_MPIC = 6,
neoVIIEVB_MPIC = 7,
neoVIPENDANT_MPIC = 8,
neoVIFIRE_VNET_MCHIP = 9,
neoVIFIRE_VNET_LCHIP = 10,
neoVIPLASMA_Core = 11,
neoVIPLASMA_HID = 12,
neoVIANALOG_MPIC = 13,
neoVIPLASMA_ANALOG_Core = 14,
neoVIPLASMA_FlexRay_Core = 15,
neoVIPLASMA_Core_1_12 = 16,
neoVIFIRE_Slave_VNET_MCHIP = 17,
neoVIFIRE_Slave_VNET_LCHIP = 18,
neoVIION_Core = 19,
neoVIION_HID = 20,
neoVIION_Core_Loader = 21,
neoVIION_HID_Loader = 22,
neoVIION_FPGA_BIT = 23,
neoVIFIRE_VNET_EP_MCHIP = 24,
neoVIFIRE_VNET_EP_LCHIP = 25,
neoVIAnalogOut_MCHIP = 26,
neoVIMOST25_MCHIP = 27,
neoVIMOST50_MCHIP = 28,
neoVIMOST150_MCHIP = 29,
ValueCAN4_4_MCHIP = 30,
ValueCAN4_4_SCHIP = 31,
cmProbe_ZYNQ = 33,
EEVB_STM32 = 34,
neoVIFIRE_Slave_VNET_EP_MCHIP = 35,
neoVIFIRE_Slave_VNET_EP_LCHIP = 36,
RADStar_MCHIP = 37,
ValueCANrf_MCHIP = 38,
neoVIFIRE2_MCHIP = 39,
neoVIFIRE2_CCHIP = 40,
neoVIFIRE2_Core = 41,
neoVIFIRE2_BLECHIP = 42,
neoVIFIRE2_ZYNQ = 43, // FIRE2 MVNET Z - Zynq
neoVIFIRE2_SECURITYCHIP = 44,
RADGalaxy_ZYNQ = 45,
neoVIFIRE2_VNET_MCHIP = 46,
neoVIFIRE2_Slave_VNET_A_MCHIP = 47,
neoVIFIRE2_Slave_VNET_A_CCHIP = 48,
neoVIFIRE2_VNET_CCHIP = 49,
neoVIFIRE2_VNET_Core = 50,
RADStar2_ZYNQ = 51,
VividCAN_MCHIP = 52,
neoOBD2SIM_MCHIP = 53,
neoVIFIRE2_VNETZ_MCHIP = 54,
neoVIFIRE2_VNETZ_ZYNQ = 55,
neoVIFIRE2_Slave_VNETZ_A_MCHIP = 56,
neoVIFIRE2_Slave_VNETZ_A_ZYNQ = 57,
VividCAN_EXT_FLASH = 58,
VividCAN_NRF52 = 59,
cmProbe_ZYNQ_Unused = 60, // Double defined
neoOBD2PRO_MCHIP = 61,
ValueCAN4_1_MCHIP = 62,
ValueCAN4_2_MCHIP = 63,
ValueCAN4_4_2EL_Core = 64,
neoOBD2PRO_SCHIP = 65,
ValueCAN4_2EL_MCHIP = 67,
neoECUAVBTSN_MCHIP = 68,
neoOBD2PRO_Core = 69,
RADSupermoon_ZYNQ = 70,
RADMoon2_ZYNQ = 71,
VividCANPRO_MCHIP = 72,
VividCANPRO_EXT_FLASH = 73,
RADPluto_MCHIP = 74,
RADMars_ZYNQ = 75,
neoECU12_MCHIP = 76,
RADIOCANHUB_MCHIP = 77,
FlexRay_VNETZ_ZCHIP = 78,
neoOBD2_LCBADGE_MCHIP = 79,
neoOBD2_LCBADGE_SCHIP = 80,
RADMoonDuo_MCHIP = 81,
neoVIFIRE3_ZCHIP = 82,
FlexRay_VNETZ_FCHIP = 83,
RADJupiter_MCHIP = 84,
ValueCAN4Industrial_MCHIP = 85,
EtherBADGE_MCHIP = 86,
RADMars_3_ZYNQ = 87,
RADGigastar_USBZ_ZYNQ = 88,
RADGigastar_ZYNQ = 89,
RAD4G_MCHIP = 90,
neoVIFIRE3_SCHIP = 91,
RADEpsilon_MCHIP = 92,
RADA2B_ZCHIP = 93,
neoOBD2Dev_MCHIP = 94,
neoOBD2Dev_SCHIP = 95,
neoOBD2SIMDoIP_MCHIP = 96,
SFPModule_88q2112_MCHIP = 97,
RADEpsilonT_MCHIP = 98,
RADEpsilonExpress_MCHIP = 99,
RADProxima_MCHIP = 100,
NewDevice57_ZCHIP = 101,
RAD_GALAXY_2_ZMPCHIP_ID = 102,
NewDevice59_MCHIP = 103,
RADMoon2_Z7010_ZYNQ = 104,
neoVIFIRE2_Core_SG4 = 105,
RADBMS_MCHIP = 106,
RADMoon2_ZL_MCHIP = 107,
RADGigastar_USBZ_Z7010_ZYNQ = 108,
neoVIFIRE3_LINUX = 109,
RADGigastar_USBZ_Z7007S_ZYNQ = 110,
VEM_01_8DW_ZCHIP = 111,
RADGalaxy_FFG_Zynq = 112,
RADMoon3_MCHIP = 113,
RADComet_ZYNQ = 114,
VEM_02_FR_ZCHIP = 115,
RADA2B_REVB_ZCHIP = 116,
RADGigastar_FFG_ZYNQ = 117,
VEM_02_FR_FCHIP = 118,
Connect_ZCHIP = 121,
SFPModule_88q2221_MCHIP = 122,
RADGALAXY2_SYSMON_CHIP = 123,
SFPModule_88q3244_MCHIP = 124,
RADCOMET3_ZCHIP = 125,
Connect_LINUX = 126,
SFPModule_lan8670_MCHIP = 127,
VEM_04_T1S_LIN_ZCHIP = 129,
RADMOONT1S_ZCHIP = 130,
RADGigastar2_ZYNQ = 131,
SFPModule_ent11100_MCHIP = 132,
RADGemini_MCHIP = 135,
Invalid = 255
enum class ChipID : icsneoc2_chip_id_t {
neoVIFIRE_MCHIP = icsneoc2_chip_id_neovifire_mchip,
neoVIFIRE_LCHIP = icsneoc2_chip_id_neovifire_lchip,
neoVIFIRE_UCHIP = icsneoc2_chip_id_neovifire_uchip,
neoVIFIRE_JCHIP = icsneoc2_chip_id_neovifire_jchip,
ValueCAN3_MCHIP = icsneoc2_chip_id_valuecan3_mchip,
neoVIECU_MPIC = icsneoc2_chip_id_neoviecu_mpic,
neoVIIEVB_MPIC = icsneoc2_chip_id_neoviievb_mpic,
neoVIPENDANT_MPIC = icsneoc2_chip_id_neovipendant_mpic,
neoVIFIRE_VNET_MCHIP = icsneoc2_chip_id_neovifire_vnet_mchip,
neoVIFIRE_VNET_LCHIP = icsneoc2_chip_id_neovifire_vnet_lchip,
neoVIPLASMA_Core = icsneoc2_chip_id_neoviplasma_core,
neoVIPLASMA_HID = icsneoc2_chip_id_neoviplasma_hid,
neoVIANALOG_MPIC = icsneoc2_chip_id_neovianalog_mpic,
neoVIPLASMA_ANALOG_Core = icsneoc2_chip_id_neoviplasma_analog_core,
neoVIPLASMA_FlexRay_Core = icsneoc2_chip_id_neoviplasma_flexray_core,
neoVIPLASMA_Core_1_12 = icsneoc2_chip_id_neoviplasma_core_1_12,
neoVIFIRE_Slave_VNET_MCHIP = icsneoc2_chip_id_neovifire_slave_vnet_mchip,
neoVIFIRE_Slave_VNET_LCHIP = icsneoc2_chip_id_neovifire_slave_vnet_lchip,
neoVIION_Core = icsneoc2_chip_id_neoviion_core,
neoVIION_HID = icsneoc2_chip_id_neoviion_hid,
neoVIION_Core_Loader = icsneoc2_chip_id_neoviion_core_loader,
neoVIION_HID_Loader = icsneoc2_chip_id_neoviion_hid_loader,
neoVIION_FPGA_BIT = icsneoc2_chip_id_neoviion_fpga_bit,
neoVIFIRE_VNET_EP_MCHIP = icsneoc2_chip_id_neovifire_vnet_ep_mchip,
neoVIFIRE_VNET_EP_LCHIP = icsneoc2_chip_id_neovifire_vnet_ep_lchip,
neoVIAnalogOut_MCHIP = icsneoc2_chip_id_neovianalogout_mchip,
neoVIMOST25_MCHIP = icsneoc2_chip_id_neovimost25_mchip,
neoVIMOST50_MCHIP = icsneoc2_chip_id_neovimost50_mchip,
neoVIMOST150_MCHIP = icsneoc2_chip_id_neovimost150_mchip,
ValueCAN4_4_MCHIP = icsneoc2_chip_id_valuecan4_4_mchip,
ValueCAN4_4_SCHIP = icsneoc2_chip_id_valuecan4_4_schip,
cmProbe_ZYNQ = icsneoc2_chip_id_cmprobe_zynq,
EEVB_STM32 = icsneoc2_chip_id_eevb_stm32,
neoVIFIRE_Slave_VNET_EP_MCHIP = icsneoc2_chip_id_neovifire_slave_vnet_ep_mchip,
neoVIFIRE_Slave_VNET_EP_LCHIP = icsneoc2_chip_id_neovifire_slave_vnet_ep_lchip,
RADStar_MCHIP = icsneoc2_chip_id_radstar_mchip,
ValueCANrf_MCHIP = icsneoc2_chip_id_valuecanrf_mchip,
neoVIFIRE2_MCHIP = icsneoc2_chip_id_neovifire2_mchip,
neoVIFIRE2_CCHIP = icsneoc2_chip_id_neovifire2_cchip,
neoVIFIRE2_Core = icsneoc2_chip_id_neovifire2_core,
neoVIFIRE2_BLECHIP = icsneoc2_chip_id_neovifire2_blechip,
neoVIFIRE2_ZYNQ = icsneoc2_chip_id_neovifire2_zynq, // FIRE2 MVNET Z - Zynq
neoVIFIRE2_SECURITYCHIP = icsneoc2_chip_id_neovifire2_securitychip,
RADGalaxy_ZYNQ = icsneoc2_chip_id_radgalaxy_zynq,
neoVIFIRE2_VNET_MCHIP = icsneoc2_chip_id_neovifire2_vnet_mchip,
neoVIFIRE2_Slave_VNET_A_MCHIP = icsneoc2_chip_id_neovifire2_slave_vnet_a_mchip,
neoVIFIRE2_Slave_VNET_A_CCHIP = icsneoc2_chip_id_neovifire2_slave_vnet_a_cchip,
neoVIFIRE2_VNET_CCHIP = icsneoc2_chip_id_neovifire2_vnet_cchip,
neoVIFIRE2_VNET_Core = icsneoc2_chip_id_neovifire2_vnet_core,
RADStar2_ZYNQ = icsneoc2_chip_id_radstar2_zynq,
VividCAN_MCHIP = icsneoc2_chip_id_vividcan_mchip,
neoOBD2SIM_MCHIP = icsneoc2_chip_id_neoobd2sim_mchip,
neoVIFIRE2_VNETZ_MCHIP = icsneoc2_chip_id_neovifire2_vnetz_mchip,
neoVIFIRE2_VNETZ_ZYNQ = icsneoc2_chip_id_neovifire2_vnetz_zynq,
neoVIFIRE2_Slave_VNETZ_A_MCHIP = icsneoc2_chip_id_neovifire2_slave_vnetz_a_mchip,
neoVIFIRE2_Slave_VNETZ_A_ZYNQ = icsneoc2_chip_id_neovifire2_slave_vnetz_a_zynq,
VividCAN_EXT_FLASH = icsneoc2_chip_id_vividcan_ext_flash,
VividCAN_NRF52 = icsneoc2_chip_id_vividcan_nrf52,
cmProbe_ZYNQ_Unused = icsneoc2_chip_id_cmprobe_zynq_unused, // Double defined
neoOBD2PRO_MCHIP = icsneoc2_chip_id_neoobd2pro_mchip,
ValueCAN4_1_MCHIP = icsneoc2_chip_id_valuecan4_1_mchip,
ValueCAN4_2_MCHIP = icsneoc2_chip_id_valuecan4_2_mchip,
ValueCAN4_4_2EL_Core = icsneoc2_chip_id_valuecan4_4_2el_core,
neoOBD2PRO_SCHIP = icsneoc2_chip_id_neoobd2pro_schip,
ValueCAN4_2EL_MCHIP = icsneoc2_chip_id_valuecan4_2el_mchip,
neoECUAVBTSN_MCHIP = icsneoc2_chip_id_neoecuavbtsn_mchip,
neoOBD2PRO_Core = icsneoc2_chip_id_neoobd2pro_core,
RADSupermoon_ZYNQ = icsneoc2_chip_id_radsupermoon_zynq,
RADMoon2_ZYNQ = icsneoc2_chip_id_radmoon2_zynq,
VividCANPRO_MCHIP = icsneoc2_chip_id_vividcanpro_mchip,
VividCANPRO_EXT_FLASH = icsneoc2_chip_id_vividcanpro_ext_flash,
RADPluto_MCHIP = icsneoc2_chip_id_radpluto_mchip,
RADMars_ZYNQ = icsneoc2_chip_id_radmars_zynq,
neoECU12_MCHIP = icsneoc2_chip_id_neoecu12_mchip,
RADIOCANHUB_MCHIP = icsneoc2_chip_id_radiocanhub_mchip,
FlexRay_VNETZ_ZCHIP = icsneoc2_chip_id_flexray_vnetz_zchip,
neoOBD2_LCBADGE_MCHIP = icsneoc2_chip_id_neoobd2_lcbadge_mchip,
neoOBD2_LCBADGE_SCHIP = icsneoc2_chip_id_neoobd2_lcbadge_schip,
RADMoonDuo_MCHIP = icsneoc2_chip_id_radmoonduo_mchip,
neoVIFIRE3_ZCHIP = icsneoc2_chip_id_neovifire3_zchip,
FlexRay_VNETZ_FCHIP = icsneoc2_chip_id_flexray_vnetz_fchip,
RADJupiter_MCHIP = icsneoc2_chip_id_radjupiter_mchip,
ValueCAN4Industrial_MCHIP = icsneoc2_chip_id_valuecan4industrial_mchip,
EtherBADGE_MCHIP = icsneoc2_chip_id_etherbadge_mchip,
RADMars_3_ZYNQ = icsneoc2_chip_id_radmars_3_zynq,
RADGigastar_USBZ_ZYNQ = icsneoc2_chip_id_radgigastar_usbz_zynq,
RADGigastar_ZYNQ = icsneoc2_chip_id_radgigastar_zynq,
RAD4G_MCHIP = icsneoc2_chip_id_rad4g_mchip,
neoVIFIRE3_SCHIP = icsneoc2_chip_id_neovifire3_schip,
RADEpsilon_MCHIP = icsneoc2_chip_id_radepsilon_mchip,
RADA2B_ZCHIP = icsneoc2_chip_id_rada2b_zchip,
neoOBD2Dev_MCHIP = icsneoc2_chip_id_neoobd2dev_mchip,
neoOBD2Dev_SCHIP = icsneoc2_chip_id_neoobd2dev_schip,
neoOBD2SIMDoIP_MCHIP = icsneoc2_chip_id_neoobd2simdoip_mchip,
SFPModule_88q2112_MCHIP = icsneoc2_chip_id_sfpmodule_88q2112_mchip,
RADEpsilonT_MCHIP = icsneoc2_chip_id_radepsilont_mchip,
RADEpsilonExpress_MCHIP = icsneoc2_chip_id_radepsilonexpress_mchip,
RADProxima_MCHIP = icsneoc2_chip_id_radproxima_mchip,
NewDevice57_ZCHIP = icsneoc2_chip_id_newdevice57_zchip,
RAD_GALAXY_2_ZMPCHIP_ID = icsneoc2_chip_id_rad_galaxy_2_zmpchip_id,
NewDevice59_MCHIP = icsneoc2_chip_id_newdevice59_mchip,
RADMoon2_Z7010_ZYNQ = icsneoc2_chip_id_radmoon2_z7010_zynq,
neoVIFIRE2_Core_SG4 = icsneoc2_chip_id_neovifire2_core_sg4,
RADBMS_MCHIP = icsneoc2_chip_id_radbms_mchip,
RADMoon2_ZL_MCHIP = icsneoc2_chip_id_radmoon2_zl_mchip,
RADGigastar_USBZ_Z7010_ZYNQ = icsneoc2_chip_id_radgigastar_usbz_z7010_zynq,
neoVIFIRE3_LINUX = icsneoc2_chip_id_neovifire3_linux,
RADGigastar_USBZ_Z7007S_ZYNQ = icsneoc2_chip_id_radgigastar_usbz_z7007s_zynq,
VEM_01_8DW_ZCHIP = icsneoc2_chip_id_vem_01_8dw_zchip,
RADGalaxy_FFG_Zynq = icsneoc2_chip_id_radgalaxy_ffg_zynq,
RADMoon3_MCHIP = icsneoc2_chip_id_radmoon3_mchip,
RADComet_ZYNQ = icsneoc2_chip_id_radcomet_zynq,
VEM_02_FR_ZCHIP = icsneoc2_chip_id_vem_02_fr_zchip,
RADA2B_REVB_ZCHIP = icsneoc2_chip_id_rada2b_revb_zchip,
RADGigastar_FFG_ZYNQ = icsneoc2_chip_id_radgigastar_ffg_zynq,
VEM_02_FR_FCHIP = icsneoc2_chip_id_vem_02_fr_fchip,
Connect_ZCHIP = icsneoc2_chip_id_connect_zchip,
SFPModule_88q2221_MCHIP = icsneoc2_chip_id_sfpmodule_88q2221_mchip,
RADGALAXY2_SYSMON_CHIP = icsneoc2_chip_id_radgalaxy2_sysmon_chip,
SFPModule_88q3244_MCHIP = icsneoc2_chip_id_sfpmodule_88q3244_mchip,
RADCOMET3_ZCHIP = icsneoc2_chip_id_radcomet3_zchip,
Connect_LINUX = icsneoc2_chip_id_connect_linux,
SFPModule_lan8670_MCHIP = icsneoc2_chip_id_sfpmodule_lan8670_mchip,
VEM_04_T1S_LIN_ZCHIP = icsneoc2_chip_id_vem_04_t1s_lin_zchip,
RADMOONT1S_ZCHIP = icsneoc2_chip_id_radmoont1s_zchip,
RADGigastar2_ZYNQ = icsneoc2_chip_id_radgigastar2_zynq,
SFPModule_ent11100_MCHIP = icsneoc2_chip_id_sfpmodule_ent11100_mchip,
RADGemini_MCHIP = icsneoc2_chip_id_radgemini_mchip,
Invalid = icsneoc2_chip_id_invalid
};
}

44
include/icsneo/icsneoc2.h
View File

@ -993,6 +993,50 @@ icsneoc2_error_t icsneoc2_script_status_diagnostic_error_code_count_get(const ic
*/
icsneoc2_error_t icsneoc2_script_status_max_coremini_size_kb_get(const icsneoc2_script_status_t* script_status, uint16_t* value);
/**
* Get the list of chip versions on the device.
*
* @param[in] device The device to query.
* @param[out] chip_versions Receives a newly allocated chip versions handle. The caller owns this handle and must free it with icsneoc2_chip_versions_free() when done.
* @param[in] refresh Whether to refresh the chip versions from the device.
* @param[out] count Receives the number of chip versions. May be NULL if not needed.
*
* @return icsneoc2_error_t icsneoc2_error_success if successful, icsneoc2_error_invalid_parameters otherwise.
*/
icsneoc2_error_t icsneoc2_device_chip_versions_enumerate(const icsneoc2_device_t* device, icsneoc2_chip_versions_t** chip_versions, bool refresh, size_t* count);
/**
* Free a chip versions handle returned by icsneoc2_device_chip_versions_enumerate().
*
* @param[in] chip_versions The chip versions handle to free. May be NULL.
*/
icsneoc2_error_t icsneoc2_chip_versions_free(icsneoc2_chip_versions_t* chip_versions);
/**
* Advance to the next chip version in an enumeration list.
*
* @param[in] chip_versions The current chip versions handle.
*
* @return The next chip version handle, or NULL at the end of the list.
*/
icsneoc2_chip_versions_t* icsneoc2_chip_versions_next(const icsneoc2_chip_versions_t* chip_versions);
/**
* Get the properties of a chip version.
*
* @param[in] chip_versions The chip versions handle to query.
* @param[out] name Pointer to a buffer to copy the null-terminated chip name into. May be NULL if the name is not needed.
* @param[in,out] name_length On input, the size of the name buffer. On output, the length of the chip name. May be NULL if the name is not needed.
* @param[out] major Pointer to receive the major version number. May be NULL.
* @param[out] minor Pointer to receive the minor version number. May be NULL.
* @param[out] maintenance Pointer to receive the maintenance version number. May be NULL.
* @param[out] build Pointer to receive the build version number. May be NULL.
*
* @return icsneoc2_error_t icsneoc2_error_success if successful, icsneoc2_error_invalid_parameters or icsneoc2_error_string_copy_failed otherwise.
*/
icsneoc2_error_t icsneoc2_chip_versions_props_get(const icsneoc2_chip_versions_t* chip_versions, char* name, size_t* name_length, uint8_t* major, uint8_t* minor, uint8_t* maintenance, uint8_t* build);
#ifdef __cplusplus
}
#endif

139
include/icsneo/icsneoc2types.h
View File

@ -444,6 +444,145 @@ typedef enum _icsneoc2_tc10_sleep_status_t {
typedef uint8_t icsneoc2_tc10_sleep_status_t;
typedef struct icsneoc2_chip_versions_t icsneoc2_chip_versions_t;
typedef enum _icsneoc2_chip_id_t {
icsneoc2_chip_id_neovifire_mchip = 0,
icsneoc2_chip_id_neovifire_lchip = 1,
icsneoc2_chip_id_neovifire_uchip = 2,
icsneoc2_chip_id_neovifire_jchip = 3,
icsneoc2_chip_id_valuecan3_mchip = 4,
icsneoc2_chip_id_neoviecu_mpic = 6,
icsneoc2_chip_id_neoviievb_mpic = 7,
icsneoc2_chip_id_neovipendant_mpic = 8,
icsneoc2_chip_id_neovifire_vnet_mchip = 9,
icsneoc2_chip_id_neovifire_vnet_lchip = 10,
icsneoc2_chip_id_neoviplasma_core = 11,
icsneoc2_chip_id_neoviplasma_hid = 12,
icsneoc2_chip_id_neovianalog_mpic = 13,
icsneoc2_chip_id_neoviplasma_analog_core = 14,
icsneoc2_chip_id_neoviplasma_flexray_core = 15,
icsneoc2_chip_id_neoviplasma_core_1_12 = 16,
icsneoc2_chip_id_neovifire_slave_vnet_mchip = 17,
icsneoc2_chip_id_neovifire_slave_vnet_lchip = 18,
icsneoc2_chip_id_neoviion_core = 19,
icsneoc2_chip_id_neoviion_hid = 20,
icsneoc2_chip_id_neoviion_core_loader = 21,
icsneoc2_chip_id_neoviion_hid_loader = 22,
icsneoc2_chip_id_neoviion_fpga_bit = 23,
icsneoc2_chip_id_neovifire_vnet_ep_mchip = 24,
icsneoc2_chip_id_neovifire_vnet_ep_lchip = 25,
icsneoc2_chip_id_neovianalogout_mchip = 26,
icsneoc2_chip_id_neovimost25_mchip = 27,
icsneoc2_chip_id_neovimost50_mchip = 28,
icsneoc2_chip_id_neovimost150_mchip = 29,
icsneoc2_chip_id_valuecan4_4_mchip = 30,
icsneoc2_chip_id_valuecan4_4_schip = 31,
icsneoc2_chip_id_cmprobe_zynq = 33,
icsneoc2_chip_id_eevb_stm32 = 34,
icsneoc2_chip_id_neovifire_slave_vnet_ep_mchip = 35,
icsneoc2_chip_id_neovifire_slave_vnet_ep_lchip = 36,
icsneoc2_chip_id_radstar_mchip = 37,
icsneoc2_chip_id_valuecanrf_mchip = 38,
icsneoc2_chip_id_neovifire2_mchip = 39,
icsneoc2_chip_id_neovifire2_cchip = 40,
icsneoc2_chip_id_neovifire2_core = 41,
icsneoc2_chip_id_neovifire2_blechip = 42,
icsneoc2_chip_id_neovifire2_zynq = 43, // FIRE2 MVNET Z - Zynq
icsneoc2_chip_id_neovifire2_securitychip = 44,
icsneoc2_chip_id_radgalaxy_zynq = 45,
icsneoc2_chip_id_neovifire2_vnet_mchip = 46,
icsneoc2_chip_id_neovifire2_slave_vnet_a_mchip = 47,
icsneoc2_chip_id_neovifire2_slave_vnet_a_cchip = 48,
icsneoc2_chip_id_neovifire2_vnet_cchip = 49,
icsneoc2_chip_id_neovifire2_vnet_core = 50,
icsneoc2_chip_id_radstar2_zynq = 51,
icsneoc2_chip_id_vividcan_mchip = 52,
icsneoc2_chip_id_neoobd2sim_mchip = 53,
icsneoc2_chip_id_neovifire2_vnetz_mchip = 54,
icsneoc2_chip_id_neovifire2_vnetz_zynq = 55,
icsneoc2_chip_id_neovifire2_slave_vnetz_a_mchip = 56,
icsneoc2_chip_id_neovifire2_slave_vnetz_a_zynq = 57,
icsneoc2_chip_id_vividcan_ext_flash = 58,
icsneoc2_chip_id_vividcan_nrf52 = 59,
icsneoc2_chip_id_cmprobe_zynq_unused = 60, // Double defined
icsneoc2_chip_id_neoobd2pro_mchip = 61,
icsneoc2_chip_id_valuecan4_1_mchip = 62,
icsneoc2_chip_id_valuecan4_2_mchip = 63,
icsneoc2_chip_id_valuecan4_4_2el_core = 64,
icsneoc2_chip_id_neoobd2pro_schip = 65,
icsneoc2_chip_id_valuecan4_2el_mchip = 67,
icsneoc2_chip_id_neoecuavbtsn_mchip = 68,
icsneoc2_chip_id_neoobd2pro_core = 69,
icsneoc2_chip_id_radsupermoon_zynq = 70,
icsneoc2_chip_id_radmoon2_zynq = 71,
icsneoc2_chip_id_vividcanpro_mchip = 72,
icsneoc2_chip_id_vividcanpro_ext_flash = 73,
icsneoc2_chip_id_radpluto_mchip = 74,
icsneoc2_chip_id_radmars_zynq = 75,
icsneoc2_chip_id_neoecu12_mchip = 76,
icsneoc2_chip_id_radiocanhub_mchip = 77,
icsneoc2_chip_id_flexray_vnetz_zchip = 78,
icsneoc2_chip_id_neoobd2_lcbadge_mchip = 79,
icsneoc2_chip_id_neoobd2_lcbadge_schip = 80,
icsneoc2_chip_id_radmoonduo_mchip = 81,
icsneoc2_chip_id_neovifire3_zchip = 82,
icsneoc2_chip_id_flexray_vnetz_fchip = 83,
icsneoc2_chip_id_radjupiter_mchip = 84,
icsneoc2_chip_id_valuecan4industrial_mchip = 85,
icsneoc2_chip_id_etherbadge_mchip = 86,
icsneoc2_chip_id_radmars_3_zynq = 87,
icsneoc2_chip_id_radgigastar_usbz_zynq = 88,
icsneoc2_chip_id_radgigastar_zynq = 89,
icsneoc2_chip_id_rad4g_mchip = 90,
icsneoc2_chip_id_neovifire3_schip = 91,
icsneoc2_chip_id_radepsilon_mchip = 92,
icsneoc2_chip_id_rada2b_zchip = 93,
icsneoc2_chip_id_neoobd2dev_mchip = 94,
icsneoc2_chip_id_neoobd2dev_schip = 95,
icsneoc2_chip_id_neoobd2simdoip_mchip = 96,
icsneoc2_chip_id_sfpmodule_88q2112_mchip = 97,
icsneoc2_chip_id_radepsilont_mchip = 98,
icsneoc2_chip_id_radepsilonexpress_mchip = 99,
icsneoc2_chip_id_radproxima_mchip = 100,
icsneoc2_chip_id_newdevice57_zchip = 101,
icsneoc2_chip_id_rad_galaxy_2_zmpchip_id = 102,
icsneoc2_chip_id_newdevice59_mchip = 103,
icsneoc2_chip_id_radmoon2_z7010_zynq = 104,
icsneoc2_chip_id_neovifire2_core_sg4 = 105,
icsneoc2_chip_id_radbms_mchip = 106,
icsneoc2_chip_id_radmoon2_zl_mchip = 107,
icsneoc2_chip_id_radgigastar_usbz_z7010_zynq = 108,
icsneoc2_chip_id_neovifire3_linux = 109,
icsneoc2_chip_id_radgigastar_usbz_z7007s_zynq = 110,
icsneoc2_chip_id_vem_01_8dw_zchip = 111,
icsneoc2_chip_id_radgalaxy_ffg_zynq = 112,
icsneoc2_chip_id_radmoon3_mchip = 113,
icsneoc2_chip_id_radcomet_zynq = 114,
icsneoc2_chip_id_vem_02_fr_zchip = 115,
icsneoc2_chip_id_rada2b_revb_zchip = 116,
icsneoc2_chip_id_radgigastar_ffg_zynq = 117,
icsneoc2_chip_id_vem_02_fr_fchip = 118,
icsneoc2_chip_id_connect_zchip = 121,
icsneoc2_chip_id_sfpmodule_88q2221_mchip = 122,
icsneoc2_chip_id_radgalaxy2_sysmon_chip = 123,
icsneoc2_chip_id_sfpmodule_88q3244_mchip = 124,
icsneoc2_chip_id_radcomet3_zchip = 125,
icsneoc2_chip_id_connect_linux = 126,
icsneoc2_chip_id_sfpmodule_lan8670_mchip = 127,
icsneoc2_chip_id_vem_04_t1s_lin_zchip = 129,
icsneoc2_chip_id_radmoont1s_zchip = 130,
icsneoc2_chip_id_radgigastar2_zynq = 131,
icsneoc2_chip_id_sfpmodule_ent11100_mchip = 132,
icsneoc2_chip_id_radgemini_mchip = 135,
icsneoc2_chip_id_maxsize, // Must be last entry, Don't use as a chip ID.
// Used for unknown or invalid chip ID
icsneoc2_chip_id_invalid = 255
} _icsneoc2_chip_id_t;
typedef uint8_t icsneoc2_chip_id_t;
#ifdef __cplusplus
}
#endif

355
test/unit/icsneoc2.cpp
View File

@ -4,6 +4,7 @@
#include <icsneo/icsneoc2messages.h>
#include "../../api/icsneoc2/icsneoc2_internal.h"
#include <icsneo/device/devicetype.h>
#include <icsneo/device/chipid.h>
#include <icsneo/communication/message/linmessage.h>
#include <icsneo/communication/message/canmessage.h>
#include <icsneo/communication/message/canerrormessage.h>
@ -713,6 +714,360 @@ TEST(icsneoc2, test_icsneoc2_netid_t)
ASSERT_EQ(icsneoc2_netid_maxsize, 571);
}
TEST(icsneoc2, test_icsneoc2_chip_id_t)
{
ASSERT_EQ(icsneoc2_chip_id_neovifire_mchip, 0);
ASSERT_EQ(icsneoc2_chip_id_neovifire_lchip, 1);
ASSERT_EQ(icsneoc2_chip_id_neovifire_uchip, 2);
ASSERT_EQ(icsneoc2_chip_id_neovifire_jchip, 3);
ASSERT_EQ(icsneoc2_chip_id_valuecan3_mchip, 4);
ASSERT_EQ(icsneoc2_chip_id_neoviecu_mpic, 6);
ASSERT_EQ(icsneoc2_chip_id_neoviievb_mpic, 7);
ASSERT_EQ(icsneoc2_chip_id_neovipendant_mpic, 8);
ASSERT_EQ(icsneoc2_chip_id_neovifire_vnet_mchip, 9);
ASSERT_EQ(icsneoc2_chip_id_neovifire_vnet_lchip, 10);
ASSERT_EQ(icsneoc2_chip_id_neoviplasma_core, 11);
ASSERT_EQ(icsneoc2_chip_id_neoviplasma_hid, 12);
ASSERT_EQ(icsneoc2_chip_id_neovianalog_mpic, 13);
ASSERT_EQ(icsneoc2_chip_id_neoviplasma_analog_core, 14);
ASSERT_EQ(icsneoc2_chip_id_neoviplasma_flexray_core, 15);
ASSERT_EQ(icsneoc2_chip_id_neoviplasma_core_1_12, 16);
ASSERT_EQ(icsneoc2_chip_id_neovifire_slave_vnet_mchip, 17);
ASSERT_EQ(icsneoc2_chip_id_neovifire_slave_vnet_lchip, 18);
ASSERT_EQ(icsneoc2_chip_id_neoviion_core, 19);
ASSERT_EQ(icsneoc2_chip_id_neoviion_hid, 20);
ASSERT_EQ(icsneoc2_chip_id_neoviion_core_loader, 21);
ASSERT_EQ(icsneoc2_chip_id_neoviion_hid_loader, 22);
ASSERT_EQ(icsneoc2_chip_id_neoviion_fpga_bit, 23);
ASSERT_EQ(icsneoc2_chip_id_neovifire_vnet_ep_mchip, 24);
ASSERT_EQ(icsneoc2_chip_id_neovifire_vnet_ep_lchip, 25);
ASSERT_EQ(icsneoc2_chip_id_neovianalogout_mchip, 26);
ASSERT_EQ(icsneoc2_chip_id_neovimost25_mchip, 27);
ASSERT_EQ(icsneoc2_chip_id_neovimost50_mchip, 28);
ASSERT_EQ(icsneoc2_chip_id_neovimost150_mchip, 29);
ASSERT_EQ(icsneoc2_chip_id_valuecan4_4_mchip, 30);
ASSERT_EQ(icsneoc2_chip_id_valuecan4_4_schip, 31);
ASSERT_EQ(icsneoc2_chip_id_cmprobe_zynq, 33);
ASSERT_EQ(icsneoc2_chip_id_eevb_stm32, 34);
ASSERT_EQ(icsneoc2_chip_id_neovifire_slave_vnet_ep_mchip, 35);
ASSERT_EQ(icsneoc2_chip_id_neovifire_slave_vnet_ep_lchip, 36);
ASSERT_EQ(icsneoc2_chip_id_radstar_mchip, 37);
ASSERT_EQ(icsneoc2_chip_id_valuecanrf_mchip, 38);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_mchip, 39);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_cchip, 40);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_core, 41);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_blechip, 42);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_zynq, 43);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_securitychip, 44);
ASSERT_EQ(icsneoc2_chip_id_radgalaxy_zynq, 45);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnet_mchip, 46);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_slave_vnet_a_mchip, 47);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_slave_vnet_a_cchip, 48);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnet_cchip, 49);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnet_core, 50);
ASSERT_EQ(icsneoc2_chip_id_radstar2_zynq, 51);
ASSERT_EQ(icsneoc2_chip_id_vividcan_mchip, 52);
ASSERT_EQ(icsneoc2_chip_id_neoobd2sim_mchip, 53);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnetz_mchip, 54);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_vnetz_zynq, 55);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_slave_vnetz_a_mchip, 56);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_slave_vnetz_a_zynq, 57);
ASSERT_EQ(icsneoc2_chip_id_vividcan_ext_flash, 58);
ASSERT_EQ(icsneoc2_chip_id_vividcan_nrf52, 59);
ASSERT_EQ(icsneoc2_chip_id_cmprobe_zynq_unused, 60);
ASSERT_EQ(icsneoc2_chip_id_neoobd2pro_mchip, 61);
ASSERT_EQ(icsneoc2_chip_id_valuecan4_1_mchip, 62);
ASSERT_EQ(icsneoc2_chip_id_valuecan4_2_mchip, 63);
ASSERT_EQ(icsneoc2_chip_id_valuecan4_4_2el_core, 64);
ASSERT_EQ(icsneoc2_chip_id_neoobd2pro_schip, 65);
ASSERT_EQ(icsneoc2_chip_id_valuecan4_2el_mchip, 67);
ASSERT_EQ(icsneoc2_chip_id_neoecuavbtsn_mchip, 68);
ASSERT_EQ(icsneoc2_chip_id_neoobd2pro_core, 69);
ASSERT_EQ(icsneoc2_chip_id_radsupermoon_zynq, 70);
ASSERT_EQ(icsneoc2_chip_id_radmoon2_zynq, 71);
ASSERT_EQ(icsneoc2_chip_id_vividcanpro_mchip, 72);
ASSERT_EQ(icsneoc2_chip_id_vividcanpro_ext_flash, 73);
ASSERT_EQ(icsneoc2_chip_id_radpluto_mchip, 74);
ASSERT_EQ(icsneoc2_chip_id_radmars_zynq, 75);
ASSERT_EQ(icsneoc2_chip_id_neoecu12_mchip, 76);
ASSERT_EQ(icsneoc2_chip_id_radiocanhub_mchip, 77);
ASSERT_EQ(icsneoc2_chip_id_flexray_vnetz_zchip, 78);
ASSERT_EQ(icsneoc2_chip_id_neoobd2_lcbadge_mchip, 79);
ASSERT_EQ(icsneoc2_chip_id_neoobd2_lcbadge_schip, 80);
ASSERT_EQ(icsneoc2_chip_id_radmoonduo_mchip, 81);
ASSERT_EQ(icsneoc2_chip_id_neovifire3_zchip, 82);
ASSERT_EQ(icsneoc2_chip_id_flexray_vnetz_fchip, 83);
ASSERT_EQ(icsneoc2_chip_id_radjupiter_mchip, 84);
ASSERT_EQ(icsneoc2_chip_id_valuecan4industrial_mchip, 85);
ASSERT_EQ(icsneoc2_chip_id_etherbadge_mchip, 86);
ASSERT_EQ(icsneoc2_chip_id_radmars_3_zynq, 87);
ASSERT_EQ(icsneoc2_chip_id_radgigastar_usbz_zynq, 88);
ASSERT_EQ(icsneoc2_chip_id_radgigastar_zynq, 89);
ASSERT_EQ(icsneoc2_chip_id_rad4g_mchip, 90);
ASSERT_EQ(icsneoc2_chip_id_neovifire3_schip, 91);
ASSERT_EQ(icsneoc2_chip_id_radepsilon_mchip, 92);
ASSERT_EQ(icsneoc2_chip_id_rada2b_zchip, 93);
ASSERT_EQ(icsneoc2_chip_id_neoobd2dev_mchip, 94);
ASSERT_EQ(icsneoc2_chip_id_neoobd2dev_schip, 95);
ASSERT_EQ(icsneoc2_chip_id_neoobd2simdoip_mchip, 96);
ASSERT_EQ(icsneoc2_chip_id_sfpmodule_88q2112_mchip, 97);
ASSERT_EQ(icsneoc2_chip_id_radepsilont_mchip, 98);
ASSERT_EQ(icsneoc2_chip_id_radepsilonexpress_mchip, 99);
ASSERT_EQ(icsneoc2_chip_id_radproxima_mchip, 100);
ASSERT_EQ(icsneoc2_chip_id_newdevice57_zchip, 101);
ASSERT_EQ(icsneoc2_chip_id_rad_galaxy_2_zmpchip_id, 102);
ASSERT_EQ(icsneoc2_chip_id_newdevice59_mchip, 103);
ASSERT_EQ(icsneoc2_chip_id_radmoon2_z7010_zynq, 104);
ASSERT_EQ(icsneoc2_chip_id_neovifire2_core_sg4, 105);
ASSERT_EQ(icsneoc2_chip_id_radbms_mchip, 106);
ASSERT_EQ(icsneoc2_chip_id_radmoon2_zl_mchip, 107);
ASSERT_EQ(icsneoc2_chip_id_radgigastar_usbz_z7010_zynq, 108);
ASSERT_EQ(icsneoc2_chip_id_neovifire3_linux, 109);
ASSERT_EQ(icsneoc2_chip_id_radgigastar_usbz_z7007s_zynq, 110);
ASSERT_EQ(icsneoc2_chip_id_vem_01_8dw_zchip, 111);
ASSERT_EQ(icsneoc2_chip_id_radgalaxy_ffg_zynq, 112);
ASSERT_EQ(icsneoc2_chip_id_radmoon3_mchip, 113);
ASSERT_EQ(icsneoc2_chip_id_radcomet_zynq, 114);
ASSERT_EQ(icsneoc2_chip_id_vem_02_fr_zchip, 115);
ASSERT_EQ(icsneoc2_chip_id_rada2b_revb_zchip, 116);
ASSERT_EQ(icsneoc2_chip_id_radgigastar_ffg_zynq, 117);
ASSERT_EQ(icsneoc2_chip_id_vem_02_fr_fchip, 118);
ASSERT_EQ(icsneoc2_chip_id_connect_zchip, 121);
ASSERT_EQ(icsneoc2_chip_id_sfpmodule_88q2221_mchip, 122);
ASSERT_EQ(icsneoc2_chip_id_radgalaxy2_sysmon_chip, 123);
ASSERT_EQ(icsneoc2_chip_id_sfpmodule_88q3244_mchip, 124);
ASSERT_EQ(icsneoc2_chip_id_radcomet3_zchip, 125);
ASSERT_EQ(icsneoc2_chip_id_connect_linux, 126);
ASSERT_EQ(icsneoc2_chip_id_sfpmodule_lan8670_mchip, 127);
ASSERT_EQ(icsneoc2_chip_id_vem_04_t1s_lin_zchip, 129);
ASSERT_EQ(icsneoc2_chip_id_radmoont1s_zchip, 130);
ASSERT_EQ(icsneoc2_chip_id_radgigastar2_zynq, 131);
ASSERT_EQ(icsneoc2_chip_id_sfpmodule_ent11100_mchip, 132);
ASSERT_EQ(icsneoc2_chip_id_radgemini_mchip, 135);
ASSERT_EQ(icsneoc2_chip_id_maxsize, 136);
ASSERT_EQ(icsneoc2_chip_id_invalid, 255);
ASSERT_EQ(sizeof(icsneoc2_chip_id_t), sizeof(uint8_t));
}
TEST(icsneoc2, test_chip_id_enum_alignment)
{
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_MCHIP), icsneoc2_chip_id_neovifire_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_LCHIP), icsneoc2_chip_id_neovifire_lchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_UCHIP), icsneoc2_chip_id_neovifire_uchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_JCHIP), icsneoc2_chip_id_neovifire_jchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN3_MCHIP), icsneoc2_chip_id_valuecan3_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIECU_MPIC), icsneoc2_chip_id_neoviecu_mpic);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIIEVB_MPIC), icsneoc2_chip_id_neoviievb_mpic);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPENDANT_MPIC), icsneoc2_chip_id_neovipendant_mpic);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_VNET_MCHIP), icsneoc2_chip_id_neovifire_vnet_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_VNET_LCHIP), icsneoc2_chip_id_neovifire_vnet_lchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_Core), icsneoc2_chip_id_neoviplasma_core);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_HID), icsneoc2_chip_id_neoviplasma_hid);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIANALOG_MPIC), icsneoc2_chip_id_neovianalog_mpic);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_ANALOG_Core), icsneoc2_chip_id_neoviplasma_analog_core);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_FlexRay_Core), icsneoc2_chip_id_neoviplasma_flexray_core);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIPLASMA_Core_1_12), icsneoc2_chip_id_neoviplasma_core_1_12);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_Slave_VNET_MCHIP), icsneoc2_chip_id_neovifire_slave_vnet_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_Slave_VNET_LCHIP), icsneoc2_chip_id_neovifire_slave_vnet_lchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_Core), icsneoc2_chip_id_neoviion_core);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_HID), icsneoc2_chip_id_neoviion_hid);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_Core_Loader), icsneoc2_chip_id_neoviion_core_loader);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_HID_Loader), icsneoc2_chip_id_neoviion_hid_loader);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIION_FPGA_BIT), icsneoc2_chip_id_neoviion_fpga_bit);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_VNET_EP_MCHIP), icsneoc2_chip_id_neovifire_vnet_ep_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_VNET_EP_LCHIP), icsneoc2_chip_id_neovifire_vnet_ep_lchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIAnalogOut_MCHIP), icsneoc2_chip_id_neovianalogout_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIMOST25_MCHIP), icsneoc2_chip_id_neovimost25_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIMOST50_MCHIP), icsneoc2_chip_id_neovimost50_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIMOST150_MCHIP), icsneoc2_chip_id_neovimost150_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_4_MCHIP), icsneoc2_chip_id_valuecan4_4_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_4_SCHIP), icsneoc2_chip_id_valuecan4_4_schip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::cmProbe_ZYNQ), icsneoc2_chip_id_cmprobe_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::EEVB_STM32), icsneoc2_chip_id_eevb_stm32);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_Slave_VNET_EP_MCHIP), icsneoc2_chip_id_neovifire_slave_vnet_ep_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE_Slave_VNET_EP_LCHIP), icsneoc2_chip_id_neovifire_slave_vnet_ep_lchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADStar_MCHIP), icsneoc2_chip_id_radstar_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCANrf_MCHIP), icsneoc2_chip_id_valuecanrf_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_MCHIP), icsneoc2_chip_id_neovifire2_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_CCHIP), icsneoc2_chip_id_neovifire2_cchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Core), icsneoc2_chip_id_neovifire2_core);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_BLECHIP), icsneoc2_chip_id_neovifire2_blechip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_ZYNQ), icsneoc2_chip_id_neovifire2_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_SECURITYCHIP), icsneoc2_chip_id_neovifire2_securitychip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGalaxy_ZYNQ), icsneoc2_chip_id_radgalaxy_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNET_MCHIP), icsneoc2_chip_id_neovifire2_vnet_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Slave_VNET_A_MCHIP), icsneoc2_chip_id_neovifire2_slave_vnet_a_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Slave_VNET_A_CCHIP), icsneoc2_chip_id_neovifire2_slave_vnet_a_cchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNET_CCHIP), icsneoc2_chip_id_neovifire2_vnet_cchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNET_Core), icsneoc2_chip_id_neovifire2_vnet_core);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADStar2_ZYNQ), icsneoc2_chip_id_radstar2_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCAN_MCHIP), icsneoc2_chip_id_vividcan_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2SIM_MCHIP), icsneoc2_chip_id_neoobd2sim_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNETZ_MCHIP), icsneoc2_chip_id_neovifire2_vnetz_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_VNETZ_ZYNQ), icsneoc2_chip_id_neovifire2_vnetz_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Slave_VNETZ_A_MCHIP), icsneoc2_chip_id_neovifire2_slave_vnetz_a_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Slave_VNETZ_A_ZYNQ), icsneoc2_chip_id_neovifire2_slave_vnetz_a_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCAN_EXT_FLASH), icsneoc2_chip_id_vividcan_ext_flash);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCAN_NRF52), icsneoc2_chip_id_vividcan_nrf52);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::cmProbe_ZYNQ_Unused), icsneoc2_chip_id_cmprobe_zynq_unused);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2PRO_MCHIP), icsneoc2_chip_id_neoobd2pro_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_1_MCHIP), icsneoc2_chip_id_valuecan4_1_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_2_MCHIP), icsneoc2_chip_id_valuecan4_2_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_4_2EL_Core), icsneoc2_chip_id_valuecan4_4_2el_core);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2PRO_SCHIP), icsneoc2_chip_id_neoobd2pro_schip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4_2EL_MCHIP), icsneoc2_chip_id_valuecan4_2el_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoECUAVBTSN_MCHIP), icsneoc2_chip_id_neoecuavbtsn_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2PRO_Core), icsneoc2_chip_id_neoobd2pro_core);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADSupermoon_ZYNQ), icsneoc2_chip_id_radsupermoon_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoon2_ZYNQ), icsneoc2_chip_id_radmoon2_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCANPRO_MCHIP), icsneoc2_chip_id_vividcanpro_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VividCANPRO_EXT_FLASH), icsneoc2_chip_id_vividcanpro_ext_flash);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADPluto_MCHIP), icsneoc2_chip_id_radpluto_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMars_ZYNQ), icsneoc2_chip_id_radmars_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoECU12_MCHIP), icsneoc2_chip_id_neoecu12_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADIOCANHUB_MCHIP), icsneoc2_chip_id_radiocanhub_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::FlexRay_VNETZ_ZCHIP), icsneoc2_chip_id_flexray_vnetz_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2_LCBADGE_MCHIP), icsneoc2_chip_id_neoobd2_lcbadge_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2_LCBADGE_SCHIP), icsneoc2_chip_id_neoobd2_lcbadge_schip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoonDuo_MCHIP), icsneoc2_chip_id_radmoonduo_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE3_ZCHIP), icsneoc2_chip_id_neovifire3_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::FlexRay_VNETZ_FCHIP), icsneoc2_chip_id_flexray_vnetz_fchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADJupiter_MCHIP), icsneoc2_chip_id_radjupiter_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::ValueCAN4Industrial_MCHIP), icsneoc2_chip_id_valuecan4industrial_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::EtherBADGE_MCHIP), icsneoc2_chip_id_etherbadge_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMars_3_ZYNQ), icsneoc2_chip_id_radmars_3_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_USBZ_ZYNQ), icsneoc2_chip_id_radgigastar_usbz_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_ZYNQ), icsneoc2_chip_id_radgigastar_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RAD4G_MCHIP), icsneoc2_chip_id_rad4g_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE3_SCHIP), icsneoc2_chip_id_neovifire3_schip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADEpsilon_MCHIP), icsneoc2_chip_id_radepsilon_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADA2B_ZCHIP), icsneoc2_chip_id_rada2b_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2Dev_MCHIP), icsneoc2_chip_id_neoobd2dev_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2Dev_SCHIP), icsneoc2_chip_id_neoobd2dev_schip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoOBD2SIMDoIP_MCHIP), icsneoc2_chip_id_neoobd2simdoip_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_88q2112_MCHIP), icsneoc2_chip_id_sfpmodule_88q2112_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADEpsilonT_MCHIP), icsneoc2_chip_id_radepsilont_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADEpsilonExpress_MCHIP), icsneoc2_chip_id_radepsilonexpress_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADProxima_MCHIP), icsneoc2_chip_id_radproxima_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::NewDevice57_ZCHIP), icsneoc2_chip_id_newdevice57_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RAD_GALAXY_2_ZMPCHIP_ID), icsneoc2_chip_id_rad_galaxy_2_zmpchip_id);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::NewDevice59_MCHIP), icsneoc2_chip_id_newdevice59_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoon2_Z7010_ZYNQ), icsneoc2_chip_id_radmoon2_z7010_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE2_Core_SG4), icsneoc2_chip_id_neovifire2_core_sg4);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADBMS_MCHIP), icsneoc2_chip_id_radbms_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoon2_ZL_MCHIP), icsneoc2_chip_id_radmoon2_zl_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_USBZ_Z7010_ZYNQ), icsneoc2_chip_id_radgigastar_usbz_z7010_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::neoVIFIRE3_LINUX), icsneoc2_chip_id_neovifire3_linux);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_USBZ_Z7007S_ZYNQ), icsneoc2_chip_id_radgigastar_usbz_z7007s_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VEM_01_8DW_ZCHIP), icsneoc2_chip_id_vem_01_8dw_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGalaxy_FFG_Zynq), icsneoc2_chip_id_radgalaxy_ffg_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMoon3_MCHIP), icsneoc2_chip_id_radmoon3_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADComet_ZYNQ), icsneoc2_chip_id_radcomet_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VEM_02_FR_ZCHIP), icsneoc2_chip_id_vem_02_fr_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADA2B_REVB_ZCHIP), icsneoc2_chip_id_rada2b_revb_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar_FFG_ZYNQ), icsneoc2_chip_id_radgigastar_ffg_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VEM_02_FR_FCHIP), icsneoc2_chip_id_vem_02_fr_fchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::Connect_ZCHIP), icsneoc2_chip_id_connect_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_88q2221_MCHIP), icsneoc2_chip_id_sfpmodule_88q2221_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGALAXY2_SYSMON_CHIP), icsneoc2_chip_id_radgalaxy2_sysmon_chip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_88q3244_MCHIP), icsneoc2_chip_id_sfpmodule_88q3244_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADCOMET3_ZCHIP), icsneoc2_chip_id_radcomet3_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::Connect_LINUX), icsneoc2_chip_id_connect_linux);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_lan8670_MCHIP), icsneoc2_chip_id_sfpmodule_lan8670_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::VEM_04_T1S_LIN_ZCHIP), icsneoc2_chip_id_vem_04_t1s_lin_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADMOONT1S_ZCHIP), icsneoc2_chip_id_radmoont1s_zchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGigastar2_ZYNQ), icsneoc2_chip_id_radgigastar2_zynq);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::SFPModule_ent11100_MCHIP), icsneoc2_chip_id_sfpmodule_ent11100_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::RADGemini_MCHIP), icsneoc2_chip_id_radgemini_mchip);
ASSERT_EQ(static_cast<icsneoc2_chip_id_t>(icsneo::ChipID::Invalid), icsneoc2_chip_id_invalid);
}
TEST(icsneoc2, test_icsneoc2_chip_versions_invalid_parameters)
{
size_t count = 0;
icsneoc2_chip_versions_t* chip_versions = nullptr;
// enumerate: NULL device
ASSERT_EQ(icsneoc2_error_invalid_parameters, icsneoc2_device_chip_versions_enumerate(NULL, &chip_versions, false, &count));
// props_get: NULL handle
uint8_t major = 0, minor = 0, maintenance = 0, build = 0;
char name[32] = {0};
size_t name_length = sizeof(name);
ASSERT_EQ(icsneoc2_error_invalid_parameters, icsneoc2_chip_versions_props_get(NULL, name, &name_length, &major, &minor, &maintenance, &build));
// free: NULL handle
ASSERT_EQ(icsneoc2_error_invalid_parameters, icsneoc2_chip_versions_free(NULL));
// next: NULL handle returns NULL
ASSERT_EQ(nullptr, icsneoc2_chip_versions_next(NULL));
}
TEST(icsneoc2, test_icsneoc2_chip_versions_props_get)
{
// Build an in-memory list of two chip_versions nodes
icsneoc2_chip_versions_t second{};
second.version_report.id = icsneo::ChipID::RADGemini_MCHIP;
second.version_report.name = "second";
second.version_report.major = 9;
second.version_report.minor = 8;
second.version_report.maintenance = 7;
second.version_report.build = 6;
second.next = nullptr;
icsneoc2_chip_versions_t first{};
first.version_report.id = icsneo::ChipID::neoVIFIRE_MCHIP;
first.version_report.name = "first";
first.version_report.major = 1;
first.version_report.minor = 2;
first.version_report.maintenance = 3;
first.version_report.build = 4;
first.next = &second;
// next() walks the list
ASSERT_EQ(&second, icsneoc2_chip_versions_next(&first));
ASSERT_EQ(nullptr, icsneoc2_chip_versions_next(&second));
// props_get: full extraction
char name[32] = {0};
size_t name_length = sizeof(name);
uint8_t major = 0, minor = 0, maintenance = 0, build = 0;
ASSERT_EQ(icsneoc2_error_success, icsneoc2_chip_versions_props_get(&first, name, &name_length, &major, &minor, &maintenance, &build));
ASSERT_STREQ(name, "first");
ASSERT_EQ(name_length, 5u);
ASSERT_EQ(major, 1);
ASSERT_EQ(minor, 2);
ASSERT_EQ(maintenance, 3);
ASSERT_EQ(build, 4);
// props_get: all output pointers optional (NULL allowed)
ASSERT_EQ(icsneoc2_error_success, icsneoc2_chip_versions_props_get(&second, NULL, NULL, NULL, NULL, NULL, NULL));
// props_get: only some output pointers
major = 0;
ASSERT_EQ(icsneoc2_error_success, icsneoc2_chip_versions_props_get(&second, NULL, NULL, &major, NULL, NULL, NULL));
ASSERT_EQ(major, 9);
// props_get: name buffer too small returns string_copy_failed
char tiny[2] = {0};
size_t tiny_length = sizeof(tiny);
ASSERT_EQ(icsneoc2_error_string_copy_failed, icsneoc2_chip_versions_props_get(&first, tiny, &tiny_length, NULL, NULL, NULL, NULL));
}
TEST(icsneoc2, test_icsneoc2_chip_versions_free_list)
{
// Allocate a two-node list the same way the API does, so free() walks and deletes it.
auto* head = new icsneoc2_chip_versions_t{};
head->version_report.name = "a";
head->next = new icsneoc2_chip_versions_t{};
head->next->version_report.name = "b";
head->next->next = nullptr;
ASSERT_EQ(icsneoc2_error_success, icsneoc2_chip_versions_free(head));
}
TEST(icsneoc2, test_icsneoc2_open_options_default)
{
icsneoc2_open_options_t expected = ICSNEOC2_OPEN_OPTIONS_GO_ONLINE | ICSNEOC2_OPEN_OPTIONS_SYNC_RTC | ICSNEOC2_OPEN_OPTIONS_ENABLE_AUTO_UPDATE;