mirror of
https://github.com/intrepidcs/libicsneo.git
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122 lines
5.2 KiB
C++
122 lines
5.2 KiB
C++
#ifndef __ERAYREGISTER_H_
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#define __ERAYREGISTER_H_
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#include <cstdint>
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namespace icsneo {
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namespace FlexRay {
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enum class ERAYRegister : uint32_t {
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// Customer Registers : Not Part of ERAY, part of FUJITSU FlexRay ASSP MB88121C
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VER = 0x0000,// Version Information Register reset = 0440_79FF Access = r
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CCNT = 0x0004,// Clock Control Register reset = 0000_0000 Access = r/w
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DBGS_DMAS = 0x0008,// Debug Support Register / DMA Support Register reset = 0000_0000 Acess = r/w
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INT_REG = 0x000C,// Interrupt Register Register reset = 0000_0000 Acess = r/w
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LCK = 0x001C,// Lock Register reset = 0000_0000 Acess = r/w
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// Interrupt-Related Registers
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EIR = 0x0020,// Error Interrupt Register reset=0000_0000 Access = r/w
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SIR = 0x0024,// Status Interrupt Register 0000_0000 r/w
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EILS = 0x0028,// Error Interrupt Line Select Register 0000_0000 r/w
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SILS = 0x002C,// Status Interrupt Line Select Register 0303_FFFF r/w
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EIES = 0x0030,// Error Interrupt Enable Register (set) 0000_0000 r/w
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EIER = 0x0034,// Error Interrupt Enable Register (reset) 0000_0000 r/w
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SIES = 0x0038,// Status Interrupt Enable Register (set) 0000_0000 r/w
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SIER = 0x003C,// Status Interrupt Enable Register (reset) 0000_0000 r/w
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ILE = 0x0040,// Interrupt Line Enable Register 0000_0000 r/w
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T0C = 0x0044,// Timer 0 Configuration Register 0 0000_0000 r/w
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T1C = 0x0048,// Timer 0 Configuration Register 1 0002_0000 r/w
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STPW1 = 0x004C,// Stop Watch Register 1 0000_0000 r/w
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STPW2 = 0x0050,// Stop Watch Register 2 0000_0000 r
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//0x0054�0x007C- reserved(11) 0000_0000 r
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// System Universal Control (SUC)
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// The system universal control controls the following functions.
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//� Configuration
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//� Wakeup
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//� Startup
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//� Normal operation
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//� Passive operation
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//� Monitor mode
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SUCC1 = 0x0080,// SUC Configuration Register 1 0C40_1000 r/w
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SUCC2 = 0x0084,// SUC Configuration Register 2 0100_0504 r/w
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SUCC3 = 0x0088,// SUC Configuration Register 3 0000_0011 r/w
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// Network Management (NEM)
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// Sets the handling of the network management vector
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NEMC = 0x008C,// NEM Configuration Register 0000_0000 r/w
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PRTC1 = 0x0090,// PRT Configuration Register 1 084C_0633 r/w
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PRTC2 = 0x0094,// PRT Configuration Register 2 0F2D_0A0E r/w
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MHDC = 0x0098,// MHD Configuration Register 0000_0000 r/w
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GTUC1 = 0x00A0,// GTU Configuration Register 1 0000_0280 r/w
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GTUC2 = 0x00A4,// GTU Configuration Register 2 0002_000A r/w
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GTUC3 = 0x00A8,// GTU Configuration Register 3 0202_0000 r/w
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GTUC4 = 0x00AC,// GTU Configuration Register 4 0008_0007 r/w
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GTUC5 = 0x00B0,// GTU Configuration Register 5 0E00_0000 r/w
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GTUC6 = 0x00B4,// GTU Configuration Register 6 0002_0000 r/w
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GTUC7 = 0x00B8,// GTU Configuration Register 7 0002_0004 r/w
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GTUC8 = 0x00BC,// GTU Configuration Register 8 0000_0002 r/w
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GTUC9 = 0x00C0,// GTU Configuration Register 9 0000_0101 r/w
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GTUC10 = 0x00C4,// GTU Configuration Register 10 0002_0005 r/w
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GTUC11 = 0x00C8,// GTU Configuration Register 11 0000_0000 r/w
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CCSV = 0x0100,// CC Status Vector Register 0010_4000 r
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CCEV = 0x0104,// CC Error Vector Register 0000_0000 r
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// 0x0108 =-0x010C, reserved(2) 0000_0000 r
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SCV = 0x0110,//Slot Counter Value Register 0000_0000 r
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MTCCV = 0x0114,//Macrotick and Cycle Counter Value Register 0000_0000 r
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RCV = 0x0118,//Rate Correction Value Register 0000_0000 r
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OCV = 0x011C,//Offset Correction Value Register 0000_0000 r
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SFS = 0x0120,//Sync Frame Status Register 0000_0000 r
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SWNIT = 0x0124,//Symbol Window and NIT Status Register 0000_0000 r
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ACS = 0x0128,//Aggregated Channel Status Register 0000_0000 r/w -
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ESID_START = 0x0130,
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ESID_END = 0x0168,
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OSID_START = 0x0170,
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OSID_END = 0x01A8,
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NMV1 = 0x01B0,
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NMV2 = 0x01B4,
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NMV3 = 0x01B8,
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// Message Buffer Control Registers
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MRC = 0x0300,// Message RAM Configuration Register 0180_0000 r/w
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FRF = 0x0304,// FIFO Rejection Filter Register 0180_0000 r/w
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FRFM = 0x0308,// FIFO Rejection Filter Mask Register 0000_0000 r/w
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FCL = 0x030C,// FIFO Critical Level Register 0000_0080 r/w
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// Message Buffer Status Registers
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MHDS = 0x0310,// Message Handler Status Register 0000_0000 r/w
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LDTS = 0x0314,// Last Dynamic Transmit Slot Register 0000_0000 r
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FSR = 0x0318,// FIFO Status Register 0000_0000 r
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MHDF = 0x031C,// Message Handler Constraints Flags Register 0000_0000 r/w
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TXRQ1 = 0x0320,// Transmission Request Register 1 0000_0000 r
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TXRQ2 = 0x0324,// Transmission Request Register 2 0000_0000 r
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TXRQ3 = 0x0328,// Transmission Request Register 3 0000_0000 r
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TXRQ4 = 0x032C,// Transmission Request Register 4 0000_0000 r
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NDAT1 = 0x0330,// New Data Register 1 0000_0000 r
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NDAT2 = 0x0334,// New Data Register 2 0000_0000 r
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ENDN = 0x03F4,// Endian check, 8765_4321 r
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WRHS1 = 0x0500,// Write Header Section Register 1
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WRHS2 = 0x0504,// Write Header Section Register 2
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WRHS3 = 0x0508,// Write Header Section Register 3
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IBCM = 0x0510,// Input Buffer Command Mask Register
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IBCR = 0x0514,// Input Buffer Command Request Register
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OBCM = 0x710,
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OBCR = 0x714,
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};
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} // namespace FlexRay
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} // namespace icsneo
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#endif // __ERAYREGISTER_H_
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